The degree of the integration, the speed of the operation and the reliability of the circuit are greatly affected by the structure for the interconnection of wiring conductors and the method of making the structure.
The conventional art of connecting multilayered wiring conductors to each other is illustrated by the teachings of Japanese Patent Application (OPI) No. 36944/84 in FIG. 1 (the term "OPI" as used herein means an "unexamined published application"). As shown in FIG. 8(a), OPI 36944/84 discloses an interlaid electric insulator film 4' made of silicon dioxide, by a chemical vapor deposition process on the whole side of a first wiring layer 2 made of aluminum on a semiconductor substrate 1, a contact hole 6 is thereafter made in the film 4' by conventional photoetching, and a second wiring layer 3 made of aluminum is connected to the first wiring layer 2 through the contact hole to perform the interconnection of the multilayer wiring conductors.
In some cases, due to an alignment failure such as the deviation of the position of a mask in the photoetching, the contact hole 6 is not provided in a position completely coincident with that of the prescribed portion of the first wiring layer 2. As a result, the contact hole not only extends on the contact portion of the first wiring layer 2, but also extends to a lower wiring layer or the substrate thus causing a short circuit in the region outside the prescribed portion.
In an effort to solve this problem, as shown in FIG. 8(b), the cross-sectional area of the contact portion of the first wiring layer 2 is provided with an allowance a beforehand so as to be larger than that of the contact hole 6 to prevent the contact hole from extending to the lower wiring layer or the substrate due to the alignment failure. However, since the crosssectional area of the contact portion of the first wiring layer 2 is provided with the allowance a, the cross-sectional area is increased and restricts the enhancement of the degree of integration. is directly deposited on the first wiring layer 2, the wall of the layer is not properly covered with the film.
Furthermore, since the interlaid electric insulator film 4' is directly deposited on the first wiring layer 2, the wall of the layer is not properly covered with the film.